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Ordering number : EN5520A
CMOS LSI
LC74785, LC74785M
On-Screen Display Controller LSI
Overview
The LC74785 and LC74785M are on-chip EDS CMOS LSIs for on-screen display, a function that displays characters and patterns on a TV screen under microprocessor control. These LSIs support 12 x 18 dot characters and can display 12 lines by 24 characters of text.
Package Dimensions
unit: mm
3067-DIP24S
[LC74785]
Features
* Display format: 24 characters by 12 rows (Up to 288 characters) * Character format: 12 (horizontal) x 18 (vertical) dots * Character sizes: Three sizes each in the horizontal and vertical directions * Characters in font: 128 * Initial display positions: 64 horizontal positions and 64 vertical positions * Blinking: Specifiable in character units * Blinking types: Two periods supported: About 1.0 second and about 0.5 second * Blanking: Over the whole font (12 x 18 dots) * Background color -- Background coloring: 8 colors (internal synchronization mode): 4fsc -- Background coloring: 6 colors (internal synchronization mode): 2fsc * Line background color -- Can be set for 3 lines -- Line background coloring: 8 colors (internal synchronization mode): 4fsc -- Line background coloring: 6 colors (internal synchronization mode): 2fsc * External control input: 8-bit serial input format * On-chip sync separator circuit * EDS support * Video output -- NTSC-format composite output * Package 24-pin plastic DIP (300 mil) 24-pin plastic SOP (375 mil)
SANYO: DIP24S
unit: mm
3045B-MFP24
[LC74785M]
SANYO: MFP24
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63097HA (OT) No. 5520-1/24
LC74785, LC74785M Pin Assignment
Pin Functions
Pin No. 1 2 Pin VSS1 Xtal IN Xtal OUT (MUTE) Crystal oscillator (MUTE input) Function Ground Notes Ground connection (digital system ground) These pins are used either to connect the crystal and capacitor used to form an external crystal oscillator used to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the Xtalout pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character border) output. This is a 3-value output. Line 21H pulse output (Even fields when MOD1 is low, both fields when MOD1 is high) Connections for the coil and capacitor that form the character output dot clock generation oscillator.
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs a field discrimination pulse (O/E pulse) when SEL2 is high.(HLFTON: Valid when 0) HLFTON: A signal in the range specified by LNA*, LNB*, and LNC* is output when HLFTON is high.) Outputs the dot clock (LC oscillator) when CS1 is high and RST is low. (This signal is not output on command resets.) Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not output on command resets.)
3
4
CTRL1 (CHABLK)
Crystal oscillator input switching (CHABLK output)
5 6 7
LN21 OSC IN OSC OUT
Data output
LC oscillator
8
SYNC JDG
External synchronizing signal judgment output
9
CS1
Enable input
Enable input pin for the OSD serial data input function. Serial data input is enabled when this pin is low. A pull-up resistor is built in. (The input has hysteresis characteristics.) Input for the serial data input clock. A pull-up resistor is built in. (The input has hysteresis characteristics.) Serial data input. A pull-up resistor is built in. (The input has hysteresis characteristics.) Composite video signal level adjustment power supply (analog system power supply) Composite video signal output Ground connection (analog system ground)
10 11 12 13 14
SCLK SIN VDD2 CVOUT VSS2
Clock input Data input Power supply Video signal output Ground
Continued on next page. No. 5520-2/24
LC74785, LC74785M
Continued from preceding page.
Pin No. 15 16 17 18 19 Pin CV IN VDD1 SYNIN CDLR SEPOUT Function Video signal input Power supply Sync separator circuit input Background color phase adjustment Composite synchronizing signal output Composite video signal input Power supply (+5 V: digital system power supply) Video signal input for the built-in sync separator circuit Background color phase adjustment. Connect to ground through a resistor and a capacitor. Video signal output for the built-in sync separator circuit. Can be switched to function as an output for signal (high or ST. pulse) due to MOD0 by setting SEL0 high. Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal. An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1 if unused. This pin can be switched to function as the frame signal input mode by setting SEL1 high. (This is valid when CTL3 is set to 1.) EDS data output enable input. EDS data output is enabled when this pin is low. A pull-up resistor is built in. (The input has hysteresis characteristics.) EDS data output (This pin can be either an n-channel open-drain output or a CMOS output.) System reset input A pull-up resistor is built in. (The input has hysteresis characteristics.) Power supply (+5 V: digital system power supply) Notes
20
SEP
IN
Vertical synchronizing signal input
21
CS2
Enable input
22
CPDT
Data output
23 24
RST VDD1
Reset input Power supply (+5 V)
Note: Both VDD1 pins must be connected to the power supply.
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD VIN VOUT Pd max Topr Tstg VDD1 and VDD2 All input pins LN21, CPDT, SEPOUT, and SYNCJDG Ta = 25C Conditions Ratings VSS-0.3 to VSS+7.0 VSS-0.3 to VDD+0.3 VSS-0.3 to VDD+0.3 350 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Symbol VDD1 VDD2 VIH1 VIH2 Input low-level voltage VIL1 VIL2 Pull-up resistance Composite video signal input voltage Input voltage RPU VIN1 VIN2 VIN3 FOSC1 Oscillator frequency FOSC1 FOSC2 VDD1 VDD2 RST, CS1, CS2, SIN, SCLK, SEPIN, and MUTE CTRL1 RST, CS1, CS2, SIN, SCLK, SEPIN, and MUTE CTRL1 Applies to pins set for the RST, CS1, CS2, SIN, SCLK, and MUTE pin options. CVIN; VDD1 = 5 V SYNIN; VDD1 = 5 V XtalIN (When external clock input is used) fin = 2 fsc or 4 fsc ; VDD1 = 5 V The XtalIN and XtalOUT oscillator pins (2 fsc: NTSC) The XtalIN and XtalOUT oscillator pins (4 fsc: NTSC) The OSCIN and OSCOUT oscillator pins (LC oscillator) 5 1.5 0.10 7.159 14.318 10 Conditions Ratings min 4.5 4.5 0.8VDD1 0.7VDD1 VSS - 0.3 VSS - 0.3 25 50 2.0 2.0 2.5 5.0 typ 5.0 5.0 max 5.5 1.27VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2VDD1 0.3VDD1 90 Unit V V V V V V k Vp-p Vp-p Vp-p MHz MHz MHz
Supply voltage
Input high-level voltage
Note: When the XtalIN pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.
No. 5520-3/24
LC74785, LC74785M Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified.
Parameter Input off leakage current Output off leakage current Output high-level voltage Output low-level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 CVIN CVOUT LN21, SYNCJDG, CPDT, and SEPOUT; VDD1 = 4.5 V, IOH = -1.0 mA LN21, SYNCJDG, CPDT, and SEPOUT; VDD1 = 4.5 V, IOL = 1.0 mA CHABLK; VDD1 = 5.0 V Three-value output voltage VO H M L Input current IIH IIL Operating mode current drain IDD1 IDD2 SYNC level VSN RST, CS1, CS2, SIN, SCLK, CTRL1, SEPIN, and MUTE; VIN = VDD1 CTRL1 and OSCIN; VIN = VSS1 VDD1; All outputs open, Xtal: 7.159 MHz, LC: 8 MHz VDD2: VDD2 = 5 V CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 *1 *2 *3 0.70 0.89 1.18 1.32 1.52 1.81 0.98 1.17 1.46 1.63 1.83 2.11 1.17 1.36 1.65 2.33 2.52 2.81 1.08 1.27 1.56 1.49 1.68 1.97 1.97 2.17 2.46 1.40 1.60 1.89 1.97 2.17 2.46 2.55 2.75 3.04 0.82 1.01 1.30 1.44 1.64 1.93 1.10 1.29 1.58 1.75 1.95 2.23 1.29 1.48 1.77 2.45 2.64 2.93 1.20 1.39 1.68 1.61 1.80 2.09 2.09 2.29 2.58 1.52 1.72 2.01 2.09 2.29 2.58 2.67 2.87 3.16 -1 30 20 0.94 1.13 1.42 1.56 1.76 2.05 1.22 1.41 1.70 1.87 2.07 2.35 1.41 1.60 1.89 2.57 2.76 3.05 1.32 1.51 1.80 1.83 1.92 2.21 2.21 2.41 2.70 1.64 1.84 2.13 2.21 2.41 2.70 2.79 2.99 3.28 3.3 1.8 0 3.5 1.0 5.0 2.3 0.8 1 Conditions Ratings min typ max 1 1 Unit A A V V V V V A A mA mA V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
Pedestal level
VPD
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Color burst low level
VCBL
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Color burst high level
VCBH
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Background color other than blue low level
VRSL0
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Background color other than blue high level
VRSH0
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Blue background color 1low level
VRSL1
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Blue background color 2 low level
VRSL2 VRSH1 VRSH2 VBK0
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Blue background color 1, 2 high level
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Frame level 0
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Frame level 1
VBK1
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Character level
VCHA
CVOUT; VDD1 = 5.0 V, VDD2 = 5.0 V
Note: 1. 2. 3.
When the sync level is 0.8 V When the sync level is 1.0 V When the sync level is 1.3 V
No. 5520-4/24
LC74785, LC74785M Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5 V OSD write (See Figure 1.)
Parameter Symbol tW(SCLK) tW(CS1) tSU(CS1) tSU(SIN) th(CS1) th(SIN) tword twt SCLK CS1 (The period when CS1 is high) CS1 SIN CS1 SIN The time to write 8 bits of data The RAM data write time Conditions Ratings min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
Minimum input pulse width
Data setup time
Data hold time
One word write time
EDS read (For the n-channel open-drain circuit, see Figure 2.)
Parameter Symbol tCKCY Minimum input pulse width tCKL tCKH Setup time Output delay time tICK tCKO SCLK SCLK SCLK SCLK CPDT Conditions Ratings min 2 1 1 10 0.5 typ max Unit s s s s s
Note: The CMOS output circuit follows the OSD timing.
First byte
Second byte
Figure 1 OSD Serial Data Input Timing
Note: CPDT goes to the high-impedance state when CS2 is high.
Figure 2 EDS Serial Output Test Conditions (For the n-channel open-drain circuit.)
No. 5520-5/24
Odd field
(Line number)
Pulse output when MOD1 is high
Even field
LC74785, LC74785M
Figure 3 O/E and LN21 Output Timing
The O/E signal is output from the SYNCJDG pin when SEL2 is high. LN21 is output for even fields when MOD1 is low and for both fields when MOD1 is high.
(Line number)
Pulse output when MOD1 is low or high
Note:
No. 5520-6/24
A pulse is output at line 21 in even fields when MOD1 is low. A pulse is output at line 21 in both fields when MOD1 is High. Caption data is transferred to the data output buffer.
LC74785, LC74785M
CS2 is switched from high to low after the decoder LSI (microcontroller) detects a falling edge on LN21.
High-impedance The previous data is output.
High-impedance
The 16 bits of caption data is output LSB first in synchronization with SCLK falling edges.
Figure 4 Transferring caption data from the LC74785/M to the decoder LSI (microcontroller): Method 1 (Basic LC74785/M usage)
Note: When extracting closed caption character data when MOD1 is high (NTSC-TV), applications must determine whether the current field is odd or even by checking the signal level output from the SYNCJDG pin (with SEL2 set high) when a falling edge is detected on LN21.
No. 5520-7/24
LC74785, LC74785M The timing of the transfer of caption data to the data output buffer is synchronized with the falling edge of the pulse output from LN21. Therefore, the software processing shown below is required if the decoder LSI (microcontroller) does not detect LN21 falling edges.
Activity within a given frame (MOD1: low)
Transfer of 16 data bits
Data in which all 16 bits are zero
Figure 5 Transferring caption data from the LC74785/M to the decoder LSI (microcontroller): Method 2 (When it is not possible to allocate a port on the decoder LSI (microcontroller) to detect falling edges on LN21.) Since data is output to the output buffer once (during the even field) when MOD1 is low, the data transfer control operation from the decoder LSI (microcontroller) must be performed at least twice in a single frame (about 32 ms). If a transfer control operation is performed twice in the same frame, the CPDT output on the second operation will be 16 bits of zero data. This allows the decoder LSI to determine that the data for the next frame has not been transferred yet.
Note: If CS2 remains low, the hardware will not be able to transfer the data to the output buffer. Therefore, the decoder LSI (microcontroller) must reset CS2 to high from low after it completes a data transfer control operation. Transfer method 2 cannot be used if MOD1 is high (NTSC-TV).
No. 5520-8/24
Serial to parallel converter Horizontal character size register Vertical character size register Output control Horizontal display position detector
Vertical display position register Blinking and reverse video control register
8-bit latch + command decode Display control register
RAM write address counter
System Block Diagram
Data output buffer
Decoder
Data slicer
Horizontal size counter Vertical size counter
Horizontal dot counter
Vertical dot counter
Blinking and reverse video control circuit
Display RAM
Horizontal display position detector
Vertical display position detector
Character control counter Line control counter
Decoder
LC74785, LC74785M
Font ROM
Synchronization determination
Data peak hold (data slice) HSYNC peak hold (HSYNC slice)
Composite sync signal separation control
Timing generator
Pedestal clamp Character output dot clock generator
Synchronizing signal generator
Character output control Background control Video output control
Shift register
No. 5520-9/24
LC74785, LC74785M Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 COMMAND0: 2 COMMAND1: 3 COMMAND2: 4 COMMAND3: 5 COMMAND4: 6 COMMAND5: 7 COMMAND6: 8 COMMAND7: 9 COMMAND8: 10 COMMAND9: 11 COMMAND10: Display memory (VRAM) write address setup command Display character data write command Vertical display start position and vertical character size setup command Horizontal display start position and horizontal character size setup command Display control setup command Display control setup command Synchronizing signal detection setup command Display control setup command Display control setup command Display control setup command Display control setup command
Display Control Command Table
First byte Command Command identification code 7 COMMAND0 Write address setup COMMAND1 Character write COMMAND2 Vertical character size and vertical display start position COMMAND3 Horizontal character size and horizontal display start position COMMAND4 Display control COMMAND5 Display control COMMAND6 Synchronizing signal detection COMMAND7 Display control COMMAND8 Display control COMMAND9 Display control COMMAND10 Display control 1 1 1 6 0 0 0 5 0 0 1 4 0 1 0 3 V3 0 VS 21 HS 21 2 V2 0 VS 20 HS 20 Data 1 V1 0 VS 11 HS 11 OSC STP NON DIS LIN SEL 1 SEL 2 LNB SEL LNC SEL 0 V0 0 VS 10 HS 10 SYS RST INT MUT CTL 3 MOD 1 MOD 2 MOD 3 7 0 at 0 6 0 c6 FS 5 0 c5 VP 5 HP 5 BLK 1 0 RN 1 0 LNA 2 LNB 2 LNC 2 Second byte Data 4 H4 c4 VP 4 HP 4 BLK 0 BCL RN 0 VNP SEL LNA 1 LNB 1 LNC 1 3 H3 c3 VP 3 HP 3 BK 1 CB SN 3 VSP SEL LNA 0 LNB 0 LNC 0 2 H2 c2 VP 2 HP 2 BK 0 PH 2 SN 2 MSK ERS LPA 2 LPB 2 LPC 2 1 H1 c1 VP 1 HP 1 RV PH 1 SN 1 MSK SEL LPA 1 LPB 1 LPC 1 0 H0 c0 VP 0 HP 0 DSP ON PH 0 SN 0 EGL LPA 0 LPB 0 LPC 0
1
0
1
1
0
LC
1 1 1 1 1 1 1
1 1 1 1 1 1 1
0 0 1 1 1 1 1
0 1 0 1 1 1 1
TST RAM MOD ERS 0 SEL 0 0 0 1 1 HLF TON MOD 0 0 1 0 1
0 0 0 0 0 0 0
BLK 2 0 RN 2 0 LNA 3 LNB 3 LNC 3
Once written, the command identification code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74785/M locks into the display character data write mode, and another first byte cannot be written. When the CS1 pin is set high, the LC74785/M is set to the COMMAND0 (display memory write address setup mode) state.
No. 5520-10/24
LC74785, LC74785M COMMAND0 (Display memory write address setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- V3 V2 V1 V0 Contents State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory line address (0 to B hexadecimal) Command 0 identification code Sets the display memory write address. Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- H4 H3 H2 H1 H0 Contents State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) Second byte identification code Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
COMMAND1 (Display character data write setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 0 0 1 0 0 0 0 Command 1 identification code Sets up display character data write mode. When this command is input, the LC74785/M locks in the display character data write mode until the CS1 pin goes high. Function Notes
No. 5520-11/24
LC74785, LC74785M Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register at c6 c5 c4 c3 c2 c1 c0 Contents State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character code (00 to 7F hexadecimal) Character attribute off Character attribute on Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
COMMAND2 Vertical display start position and vertical character size setup command First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- VS21 VS20 VS11 VS10 Contents State 1 0 1 0 0 1 0 1 0 1 0 1
VS11 VS21 VS20
Function Command 2 identification code Sets the vertical display start position and the vertical character size
Notes
0 1H/dot 3H/dot
1 2H/dot 1H/dot 1 2H/dot 1H/dot First line vertical character size Second line vertical character size
0 1
VS10
0 1H/dot 3H/dot
0 1
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- FS VP5 (MSB) VP4 VP3 VP2 VP1 VP0 (LSB) Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character display area Second byte identification bit Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: 5 VS = H x (2 2n VPn) n=0 H: the horizontal synchronization pulse period The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H. Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-12/24
LC74785, LC74785M COMMAND3 (Horizontal display start position and horizontal size setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- HS21 HS20 HS11 HS10 Contents State 1 0 1 1 0 1 0 1 0 1 0 1 HS11 0 1 HS21 0 1 HS10 HS20 0 1Tc/dot 3Tc/dot 0 1Tc/dot 3Tc/dot 1 2Tc/dot 1Tc/dot 1 2Tc/dot 1Tc/dot First line horizontal character size Second line horizontal character size Command 3 identification code Sets the horizontal display start position and the horizontal character size. Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- LC HP5 (MSB) HP4 HP3 HP2 HP1 HP0 (LSB) Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Second byte identification bit Use the LC oscillator for the dot clock Use the crystal oscillator for the dot clock If HS is the horizontal start position then: 5 HS = Tc x (2 2n HPn) n=0 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc. Selects the dot clock used for character display in the horizontal direction. Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-13/24
LC74785, LC74785M COMMAND4 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- TSTMOD RAMERS OSCSTP SYSRST Contents State 1 1 0 0 0 1 0 1 0 1 0 1 Reset all registers and turn display off. Erase display RAM. (Set the RAM data to 7F hexadecimal.) Do not stop the crystal and LC oscillators. Stop the crystal and LC oscillators. Normal operating mode Test mode This bit must be set to 0. Erasing RAM takes about 500 s. (This operation must be executed in the DSPOFF state.) Valid in external synchronization mode when character display is off. The registers are reset when the CS1 pin is low, and the reset state is cleared when CS1 is set high, Command 4 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- BLK2 BLK1 BLK0 BK1 BK0 RV DSPON Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
BLK1
Function Second byte identification bit Character display area Video display area
BLK0
Notes
Specifies the size for complete fill in 0 Blanking off 1 Character size Changes the blanking size
0 1 Blinking period: About 0.5 s Blinking period: About 1.0 s Blinking off Blinking on
Border size Full character size Switches the blinking period Blinking in reverse video mode switches the display between normal character display and reverse video display.
Reverse (character reversing) off Reverse (character reversing) on Character display off Character display on
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-14/24
LC74785, LC74785M COMMAND5 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- HLFTON NON INT Contents State 1 1 0 1 0 0 1 0 1 0 1 External synchronizing signal judgment output signal A signal in the range specified by LNA*, LNB*, and LNC* is output. Interlaced Noninterlaced External synchronization Internal synchronization Switches the SYNCJDG (pin 8) output. Switches between interlaced and noninterlaced video. Switches between external and internal synchronization Command 5 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- BCL CB Contents State 0 0 0 0 1 0 1 0 2 PH2 1 0 1 PH1 1 0 0 PH0 1 Background coloring on No background coloring (Only the background level is set) Color burst signal output. Color burst signal output stopped. PH2 0 0 0 0 1 1 1 1 PH1 0 0 1 1 0 0 1 1 PH0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Background color specification Only valid when BCL is high. Only valid in internal synchronization mode. Second byte identification bit Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-15/24
LC74785, LC74785M COMMAND6 (Synchronizing signal detection setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- SEL0 MOD0 DISLIN MUT Contents State 1 1 1 0 0 1 0 1 0 1 0 1 Sync separator signal Output signal set by MOD0 High-level output ST pulse signal 12 lines 10 lines Normal output CVIN is cut and CVOUT is held at the pedestal level. CVOUT switching Switches the number of lines displayed. Only valid when SEL0 is high. Switches the SEPOUT (pin 19) output. Command 6 identification code Sets up synchronizing signal control. Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- RN2 RN1 RN0 SN3 SN2 SN1 SN0 Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SN3 0 0 0 0 1 SN2 0 0 0 1 0 SN1 0 0 1 0 0 SN0 0 1 0 0 0 Number of times HSYNC detected Not detected 32 times 64 times 128 times 256 times External synchronizing signal detection control Signal present signal absent transition detection Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H). Second byte identification bit RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of times HSYNC detected 0 times 4 times 8 times 16 times External synchronizing signal detection control Signal absent signal present transition detection Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H). Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-16/24
LC74785, LC74785M COMMAND7 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- SEL1 CTL3 Contents State 1 1 1 1 0 0 0 1 0 1 Extended command 0 identification code Vertical synchronizing signal (external V separation) input Frame signal input Use internal V separation. Do not use internal V separation. Switches V separation. Switches the SEPIN (pin 20) input. Only valid when CTL3 is high. Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- VNPSEL VSPSEL MSKERS MSKSEL EGL Contents State 0 0 0 0 1 0 1 0 1 0 1 0 1 V falling edge detection V rising edge detection VSEP: about 8.9 s VSEP: about 17.8 s Mask valid Mask invalid 3H 20H Border level 0 only (VBK0) Two-stage border level (VBK0 and VBK1) Switches the VSYNC mask. Switches the border level. (Only valid when BLK0 is 0 and BLK1 is 1.) Clears the HSYNC and VSYNK masks. Switches the internal V separation period. Switches the V acquisition polarity in external mode when internal V separation is used. Second byte identification bit Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-17/24
LC74785, LC74785M COMMAND8 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- SEL2 MOD1 Contents State 1 1 1 1 0 1 0 1 0 1 Extended command 1 identification code External synchronizing signal judgment output signal O/E signal Even field line 21 data extraction (VCR) Line 21 data extraction on both odd and even fields (NTSC-TV) Switches the SYNCJDG (pin 8) output Valid when HLFTON is low. Switches line 21 data extraction. Command 8 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNA3 1 0 5 LNA2 1 0 4 LNA1 1 0 3 LNA0 1 0 2 LPA2 1 0 1 LPA1 1 0 0 LPA0 1 LPA2 0 0 0 0 1 1 1 1 LPA1 0 0 1 1 0 0 1 1 LPA0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Specifies the background color. Second byte identification bit LNA3 LNA2 LNA1 LNA0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.) Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-18/24
LC74785, LC74785M COMMAND9 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 Register -- -- -- -- -- -- LNBSEL Contents State 1 1 1 1 1 0 0 1 0 1 Extended command 2 identification code Normal line background color operation RV characters have the background color specified by PH* or the RV character background color is white. LNBSEL: 1 setting specification RV characters have the background color specified by PH*, characters are white. Valid when LNBSEL is high Switches the RV mode background color for the line specified by LNB* for characters specified for RV display. Command 9 identification code Display control setup Function Notes
0
MOD2
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNB3 1 0 5 LNB2 1 0 4 LNB1 1 0 3 LNB0 1 0 2 LPB2 1 0 1 LPB1 1 0 0 LPB0 1 LPB2 0 0 0 0 1 1 1 1 LPB1 0 0 1 1 0 0 1 1 LPB0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Specifies the background color. Second byte identification bit LNB3 LNB2 LNB1 LNB0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.) Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-19/24
LC74785, LC74785M COMMAND10 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 Register -- -- -- -- -- -- LNCSEL Contents State 1 1 1 1 1 0 0 1 0 1 Extended command 2 identification code Normal line background color operation RV characters have the background color specified by PH* or the RV character background color is white. LNCSEL: 1 setting specification RV characters have the background color specified by PH*, characters are white. Valid when LNCSEL is high Switches the RV mode background color for the line specified by LNC* for characters specified for RV display. Command 10 identification code Display control setup Function Notes
0
MOD3
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNC3 1 0 5 LNC2 1 0 4 LNC1 1 0 3 LNC0 1 0 2 LPC2 1 0 1 LPC1 1 0 0 LPC0 1 LPC2 0 0 0 0 1 1 1 1 LPC1 0 0 1 1 0 0 1 1 LPC0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Specifies the background color. Second byte identification bit LNC3 LNC2 LNC1 LNC0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (If the same line is specified to have different background colors with LNA*, LNB*, and LNC*, then the setting specified by the last command issued will be valid. The previously specification registers (LN* and LP*) will all be reset to 0.) Function Notes
Note: All registers are set to 0 when the LC74785/M is reset by the RST pin.
No. 5520-20/24
LC74785, LC74785M Display Screen Structure The display consists of 12 lines of 24 characters. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced when enlarged characters are displayed. Display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses)
24 Characters
12 Rows
No. 5520-21/24
LC74785, LC74785M Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 = 5.00 V)
Output level VCHA: Character
Output voltage (1) [V] 2.67 2.45
Output voltage (2) [V] 2.87 2.64
Output voltage (3) [V] 3.16 2.93
VRSH0: High for background colors other than blue VRSH1,2 High for blue background colors 1 and 2 VBK1: VCBH: Border 1 High for the color burst signal
2.09 2.09 1.75
2.29 2.29 1.95
2.58 2.58 2.23
VRSL2: Low for blue background color 2 VBK0: VPD: Border 0 Pedestal level
1.61 1.52 1.44 1.29
1.80 1.72 1.64 1.48
2.09 2.01 1.93 1.77
VRSL0: Low for background colors other than blue VRSL1 VCBL: VSN: Low for blue background color 1 Low for the color burst signal Sync
1.20
1.39
1.68
1.10 0.82
1.29 1.01
1.58 1.30
Note: VDD2 = 5.0 V.
No. 5520-22/24
LC74785, LC74785M Sample Application Circuit (When the LC74785/M is used in conjunction with a single-chip Y/C circuit.) External system clock input
Crystal oscillator
External system clock input (when the pin 3 and 4 functions are modified by mask options)
Note: When a sync tip level of 1.3 V DC (CVIN input signal: sync tip = 1.3 V) is selected for the internal generated video signals by option settings, the electrolytic capacitor connected to SYNIN must be connected with the correct polarity. When VDD1 is 5.0 V, the SYNIN input video signal pedestal level is clamped at about 2.5 V DC.
Microprocessor
Microprocessor
Microprocessor
No. 5520-23/24
LC74785, LC74785M
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1997. Specifications and information herein are subject to change without notice. No. 5520-24/24

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